Packaging substrate and semiconductor package
US8810045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Oct 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate and a semiconductor package each include: a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant formed in the first openings; a second encapsulant formed in the second openings; and a surface circuit layer formed on the first encapsulant and the first core circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.