Semiconductor device and method with greater epitaxial growth on 110 crystal plane
US8815656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2012 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Nov 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor processing method is provided which promotes greater growth on <110> crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on <110> crystallographic planes and the least amount of growth occurs on <100> crystallographic planes. The process can be applied to form embedded stressor regions in planar field effect transistors, and the process can be used to grow semiconductor layers on exposed wall surfaces of adjacent fins in source-drain regions of finFETs to fill spaces between the fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.