Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
US8815669B2 · kind B2 · utility
7Cited by
11References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Feb 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.