Asymmetric mesh NoC topologies
US8819611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations described herein are directed to a floor plan for a Network on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non-uniform shapes and dimensions. An interconnection network is synthesized along with a plan for a physical layout of the interconnection network based on physical dimensions of the plurality of on chip blocks, the physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan. Porosity information for the plurality of on chip blocks on the floorplan and required chip functionality may also be taken into consideration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.