Asymmetric mesh NoC topologies
US8819616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2013 |
| Grant date | Aug 26, 2014 |
| Priority date | — |
| Expiry date | Sep 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.