Select gate formation for nanodot flat cell
US8823075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2012 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Jan 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating a memory device include forming a tunnel oxide layer over a memory cell area of a semiconductor substrate, forming a floating gate layer over the tunnel oxide layer in the memory cell area, the floating gate layer comprising a plurality of nanodots embedded in a dielectric material, forming a blocking dielectric layer over the floating gate layer in the memory cell area, removing portions of the blocking dielectric layer, the floating gate layer, the tunnel oxide layer, and the semiconductor substrate in the memory cell area to form a first plurality of isolation trenches, and forming isolation material within the first plurality of isolation trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.