Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
US8828851B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
Abstract
An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.