Variable impedance memory device structure and method of manufacture including programmable impedance memory cells and methods of forming the same
US8829482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Dec 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.