Method of reading and writing nonvolatile memory cells
US8830761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Mar 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.