Compact routing
US8832632B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 25, 2012 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Oct 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for compacting routing in lower level blocks to free routing resources for upper level blocks are disclosed. In some embodiments, a specification of a hierarchical integrated circuit design comprising a lower level block and an upper level block is obtained. The specification includes an initial routing plan for the lower level block. Subsequently, a compacted routing plan for the lower level block using constrained routing resources comprising fewer routing tracks than the initial routing plan and resulting in at least one unused track as well as a routing plan for the upper level block using the at least one unused track are generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.