Semiconductor structure and method for interconnection of integrated circuits
US8841752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Jan 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one or more embodiments, a semiconductor structure is provided that includes a plurality of interposer dice on an un-singulated segment of a semiconductor wafer. Scribe lanes circumscribing each of the plurality of interposer dice have widths of at least 2.5% of the width of each interposer die. Each interposer die includes a first contact array formed on a first side of the interposer die, a plurality of vias formed through the interposer die, one or more wiring layers formed on the first side of the interposer die and electrically coupling the first contact array to the plurality of vias, and a second contact array formed on a second side of the interposer die and electrically coupled to the plurality of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.