Vertical NAND device with low capacitance and silicided word lines
US8847302B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Sep 30, 2014 |
| Priority date | — |
| Expiry date | Apr 10, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three dimensional memory device including a substrate and a semiconductor channel. At least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of the substrate. The device also includes at least one charge storage region located adjacent to semiconductor channel and a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level. Each of the plurality of control gate electrodes includes a first edge surface which is substantially free of silicide, the first edge surface facing the semiconductor channel and the at least one charge storage region and a silicide located on remaining surfaces of the control gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.