Patent · US Active

Method of making vertical transistor with graded field plate dielectric

US8853029B2 · kind B2 · utility

4Cited by

6References

7Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Marie Denison · Plano, US
Sameer Pendharkar · Allen, US
Philip L. Hower · Concord, US
John Lin

Key dates

Filing date	Jul 21, 2011
Grant date	Oct 7, 2014
Priority date	—
Expiry date	Sep 20, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/516

Abstract

An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.