Data cache block deallocate requests
US8856455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2012 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Nov 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.