Method of fabricating land grid array semiconductor package
US8860207B2 · kind B2 · utility
4Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Feb 10, 2014 |
| Grant date | Oct 14, 2014 |
| Priority date | — |
| Expiry date | Feb 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.