Current-limiting layer and a current-reducing layer in a memory device
US8866121B2 · kind B2 · utility
10Cited by
94References
17Claims
0Family size
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Key dates
| Filing date | Feb 17, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Feb 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.