Non-Volatile memory with silicided bit line contacts
US8866213B2 · kind B2 · utility
4Cited by
14References
15Claims
0Family size
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Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jan 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.