Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier
US8872252B2 · kind B2 · utility
2Cited by
1References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2011 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Feb 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02057
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.