Data cache block deallocate requests in a multi-level cache hierarchy
US8874852B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2012 |
| Grant date | Oct 28, 2014 |
| Priority date | — |
| Expiry date | Dec 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.