Shared bit line string architecture
US8879331B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for programming and reading memory cells using a shared bit line string architecture are described. In some embodiments, memory cells and select devices may correspond with transistors including a charge storage layer. In some cases, the charge storage layer may be conductive (e.g., a polysilicon layer as used in a floating gate device) or non-conductive (e.g., a silicon nitride layer as used in a SONOS device). In some embodiments, selection of a memory cell in a first string of a pair of strings may include setting an SEO transistor into a conducting state and setting an SGD line controlling drain-side select transistors to a voltage that is greater than a first threshold voltage associated with a first drain-side select transistor of the first string and less than a second threshold voltage associated with a second drain-side select transistor of a second string of the pair of strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.