Methods for improving double patterning route efficiency
US8881083B1 · kind B1 · utility
16Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2013 |
| Grant date | Nov 4, 2014 |
| Priority date | — |
| Expiry date | May 25, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design methodology for routing for an integrated circuit is disclosed. The method includes placement of cells having double diffusion breaks, which create an extended intercell region. Metal layer prohibit zones are defined to prohibit any M1 structures in the prohibit zones. Metal layer allow zones are placed adjacent to outer metal lines, and jogs are formed in the metal layer allow zones. Vias and viabars may then be applied on the jogs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.