Magnetoresistive logic cell and method of use
US8891291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Nov 18, 2014 |
| Priority date | — |
| Expiry date | Mar 18, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/935
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.