Plasma etch method to reduce micro-loading
US8901004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2010 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Oct 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3065
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing plurality of etched features in an electronic device is disclosed that avoids micro-loading problems thus maintaining more uniform sidewall profiles and more uniform critical dimensions. The method comprises performing a first time-divisional plasma etch process step within a plasma chamber to a first depth of the plurality of etched features, and performing a flash process step to remove any polymers from exposed surfaces of the plurality of etched features without requiring an oxidation step. The flash process step is performed independently of the time-divisional plasma etch step. A second time-divisional plasma etch process step is performed within the plasma chamber to a second depth of the plurality of etched features. The method may be repeated until a desired etch depth is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.