Nonvolatile memory cells with a vertical selection gate of variable depth
US8901634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2013 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Mar 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0425
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.