Adjusting reference resistances in determining MRAM resistance states
US8902641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Dec 2, 2014 |
| Priority date | — |
| Expiry date | Dec 31, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.