Aspect ratio dependent deposition to improve gate spacer profile, fin-loss and hardmask-loss for FinFET scheme
US8906760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Dec 9, 2014 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques disclosed herein include systems and methods for an aspect ratio dependent deposition process that improves gate spacer profile, reduces fin loss, and also reduces hardmask loss in a FinFET or other transistor scheme. Techniques include depositing an aspect ratio dependent protective layer to help tune profile of a structure during fabrication. Plasma and process gas parameters are tuned such that more polymer can collect on surfaces of a structure that are visible to the plasma. For example, upper portions of structures can collect more polymer as compared to lower portions of structures. The variable thickness of the protection layer enables selective portions of spacer material to be removed while other portions are protected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.