Read operations and circuits for memory devices having programmable elements, including programmable resistance elements
US8913444B1 · kind B1 · utility
6Cited by
10References
29Claims
0Family size
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Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Dec 16, 2014 |
| Priority date | — |
| Expiry date | Nov 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.