Superior integrity of high-k metal gate stacks by capping STI regions

US8916433B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Thilo Scheiper · Dresden, DE
• Peter Baars · Dresden, DE
• Sven Beyer · Dresden, DE

Key dates

• Filing date: Feb 28, 2012
• Grant date: Dec 23, 2014
• Expiry date: Jul 17, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0133
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.