Interconnect formation using a sidewall mask layer
US8916472B2 · kind B2 · utility
4Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2012 |
| Grant date | Dec 23, 2014 |
| Priority date | — |
| Expiry date | Apr 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.