Accommodating balance of bit line and source line resistances in magnetoresistive random access memory
US8923040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2013 |
| Grant date | Dec 30, 2014 |
| Priority date | — |
| Expiry date | Mar 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1697
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.