Memory with multiple word line design
US8929153B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are various apparatuses and methods for a memory with a multiple read word line design. A memory may include a plurality of bit cells arranged in a row, a first read word line connected to a first subset of the plurality of bit cells, and a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells. A method may include asserting, during a first read operation, a first read word line connected to a first subset of a plurality of bit cells arranged in a row of bit cells, and asserting, during a second read operation, a second read word line connected to a second subset of the plurality of bit cells, wherein the first and second subsets are located in the same row of bit cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.