Patent · US Active

Semiconductor gate structure for threshold voltage modulation and method of making same

US8932923B2 · kind B2 · utility

8Cited by
0References
15Claims
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Key dates

Filing dateFeb 19, 2013
Grant dateJan 13, 2015
Priority date—
Expiry dateFeb 19, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.