Memory cell floating gate replacement
US8932948B2 · kind B2 · utility
1Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2013 |
| Grant date | Jan 13, 2015 |
| Priority date | — |
| Expiry date | May 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory chip is formed by depositing two N-type polysilicon layers. The upper N-type polysilicon layer is then replaced with P-type polysilicon and barrier layer in the array area only, while maintaining the upper N-type polysilicon layer in the periphery. In this way, floating gates are substantially P-type while gates of peripheral transistors are N-type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.