Semiconductor fin isolation by a well trapping fin portion

US8933528B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Henry K. Utomo · Ridgefield, US
• Kangguo Cheng · Schenectady, US
• Ramachandra Divakaruni · Ossining, US
• Ravikumar Ramachandran · Beacon, US
• Huiling Shang · Bethlehem, US
• Reinaldo Vega · Mahopac, US

Key dates

• Filing date: Mar 11, 2013
• Grant date: Jan 13, 2015
• Expiry date: Mar 11, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.