Method to reduce magnetic film stress for better yield

US8933542B2 · kind B2 · utility

Assignee

• Headway Technologies, Inc. · US

Inventors

• Tom Zhong · Saratoga, US
• Kenlin Huang · Fremont, US
• Chyu-Jiuh Torng · Pleasanton, US

Key dates

• Filing date: Aug 7, 2014
• Grant date: Jan 13, 2015
• Expiry date: Aug 7, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/01

Abstract

A thin-film deposition, such as an MTJ (magnetic tunneling junction) layer, on a wafer-scale CMOS substrate, is segmented by walls or trenches and not affected by thin-film stresses due to wafer warpage or other subsequent annealing processes. An interface layer on the CMOS substrate is patterned by either undercut trenches extending into its upper surface or by T-shaped walls that extend along its upper surface. The thin-film is deposited continuously over the patterned surface, whereupon either the trenches or walls segment the deposition and serve as stress-relief mechanisms to eliminate adverse effects of processing as stresses such as those caused by wafer warpage.