Far back end of the line metallization method and structures

US8937009B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Timothy H. Daubenspeck · Colchester, US
• Jeffrey P. Gambino · Gresham, US
• Karen P. McLaughlin · Poughkeepsie, US
• Ekta Misra · Hillsboro, US
• Christopher D. Muzzy · Burlington, US
• Eric D. Perfecto · Wappingers Falls, US
• Wolfgang Sauter · Avon, US

Key dates

• Filing date: Apr 25, 2013
• Grant date: Jan 20, 2015
• Expiry date: Apr 25, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1305
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).