Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

US8940595B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bhupesh Chandra · Jersey City, US
• Paul Chang · Mahopac, US
• Gregory G. Freeman · Hopewell Junction, US
• Dechao Guo · Niskayuna, US
• Judson R. Holt · Wappingers Falls, US
• Arvind Kumar · Beaverton, US
• Timothy J. McArdle · Ballston Lake, US
• Shreesh Narasimha · Beacon, US
• Viorel Ontalus · Danbury, US
• Sangameshwar Rao Saudari · Hopewell Junction, US
• Christopher D. Sheraw · Wappingers Falls, US
• Matthew W. Stoker · Poughkeepsie, US

Key dates

• Filing date: Mar 15, 2013
• Grant date: Jan 27, 2015
• Expiry date: Mar 15, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.