Methods for fabricating integrated circuits with improved patterning schemes
US8940641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2013 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Sep 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76816
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating integrated circuits with improved patterning schemes are provided. In an embodiment, a method for fabricating an integrated circuit includes depositing an interlayer dielectric material overlying a semiconductor substrate. Further, the method includes forming a patterned hard mask overlying the interlayer dielectric material. Also, the method forms an organic planarization layer overlying the patterned hard mask and contacting portions of the interlayer dielectric material. The method patterns the organic planarization layer using an extreme ultraviolet (EUV) lithography process. The method also includes etching the interlayer dielectric material using the patterned hard mask and organic planarization layer as a mask to form vias in the interlayer dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.