Taejoon Han
17Patents
5h-index
32Co-inventors
62Inventor score
Filing activity: Oct 4, 2000 → Apr 11, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9252238B1 | Semiconductor structures with coplanar recessed gate layers and fabrication methods | Electricity | 405 | Active |
| US6823815B2 | Wafer area pressure control for plasma confinement | Electricity | 49 | Expired |
| US6492774B1 | Wafer area pressure control for plasma confinement | Electricity | 24 | Expired |
| US9147680B2 | Integrated circuits having replacement metal gates with improved threshold voltage performance and methods for fabricating the same | Electricity | 8 | Active |
| US7782591B2 | Methods of and apparatus for reducing amounts of particles on a wafer during wafer de-chucking | Electricity | 6 | Active |
| US9040380B2 | Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same | Electricity | 5 | Active |
| US7470627B2 | Wafer area pressure control for plasma confinement | Electricity | 4 | Expired |
| US8283255B2 | In-situ photoresist strip during plasma etching of active hard mask | Electricity | 3 | Active |
| US9401263B2 | Feature etching using varying supply of power pulses | Electricity | 1 | Active |
| US7001529B2 | Pre-endpoint techniques in photoresist etching | Electricity | 1 | Expired |
| US10215704B2 | Computed tomography using intersecting views of plasma using optical emission spectroscopy during plasma processing | Electricity | 1 | Active |
| US8940641B1 | Methods for fabricating integrated circuits with improved patterning schemes | Electricity | 1 | Active |
| US9034767B1 | Facilitating mask pattern formation | Electricity | 0 | Active |
| US8912633B2 | In-situ photoresist strip during plasma etching of active hard mask | Electricity | 0 | Active |
| US8124516B2 | Trilayer resist organic layer etch | Electricity | 0 | Active |
| US7211518B2 | Waferless automatic cleaning after barrier removal | Emerging Cross-Sectional Technologies | 0 | Expired |
| US10503850B2 | Generation of a map of a substrate using iterative calculations of non-measured attribute data | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.