Low threshold voltage CMOS device
US8941184B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Jan 27, 2015 |
| Priority date | — |
| Expiry date | Dec 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.