High linearity SOI wafer for low-distortion circuit applications

US8951896B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Alan B. Botula · South Burlington, US
• Jeffrey E. Hanrahan · Burlington, US
• Mark D. Jaffe · Shelburne, US
• Alvin J. Joseph · Williston, US
• Dale W. Martin · Hyde Park, US
• Gerd Pfeiffer · Poughquag, US
• James A. Slinkman · Montpelier, US

Key dates

• Filing date: Jun 28, 2013
• Grant date: Feb 10, 2015
• Expiry date: Jun 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/324
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to a method herein, a first side of a substrate is implanted with a first material to change a crystalline structure of the first side of the substrate from a first crystalline state to a second crystalline state, after the first material is implanted. A second material is deposited on the first side of the substrate, after the first material is implanted. A first side of an insulator layer is bonded to the second material on the first side of the substrate. Integrated circuit devices are formed on a second side of the insulator layer, opposite the first side of the insulator layer, after the insulator layer is bonded to the second material. The integrated circuit devices are thermally annealed. The first material maintains the second crystalline state of the first side of the substrate during the annealing.