Stacked multi-chip bottom source semiconductor device and preparation method thereof
US8952509B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2013 |
| Grant date | Feb 10, 2015 |
| Priority date | — |
| Expiry date | Sep 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.