Patent · US Active

Using an integrated circuit die configuration for package height reduction

US8957510B2 · kind B2 · utility

0Cited by

6References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Tim V. Pham · Austin, US
James R. Guajardo · Georgetown, US
Michael B. McShane · Austin, US

Key dates

Filing date	Jul 3, 2013
Grant date	Feb 17, 2015
Priority date	—
Expiry date	Jul 3, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18165
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.