Method for manufacturing a semiconductor-on-insulator structure having low electrical losses
US8962450B2 · kind B2 · utility
3Cited by
8References
16Claims
0Family size
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Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.