Daniel Delprat
24Patents
5h-index
34Co-inventors
69Inventor score
Filing activity: May 31, 2001 → Apr 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6563631B2 | Tunable gain-clamped semiconductor optical amplifier | Electricity | 27 | Expired |
| US7405136B2 | Methods for manufacturing compound-material wafers and for recycling used donor substrates | Electricity | 15 | Active |
| US6459158B1 | Vertically-tolerant alignment using slanted wall pedestal | Physics | 7 | Expired |
| US7645682B2 | Bonding interface quality by cold cleaning and hot bonding | Electricity | 6 | Active |
| US8580654B2 | Method for molecular bonding of silicon and glass substrates | Electricity | 5 | Active |
| US8357974B2 | Semiconductor on glass substrate with stiffening layer and process of making the same | Electricity | 5 | Active |
| US8790993B2 | Method for molecular bonding of silicon and glass substrates | Electricity | 3 | Active |
| US9716029B2 | Method for transferring a layer of a semiconductor and substrate comprising a confinement structure | Electricity | 3 | Active |
| US8962450B2 | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses | Electricity | 3 | Active |
| US8349703B2 | Method of bonding two substrates | Electricity | 2 | Active |
| US7485545B2 | Method of configuring a process to obtain a thin layer with a low density of holes | Electricity | 2 | Active |
| US10826459B2 | Heterostructure and method of fabrication | Emerging Cross-Sectional Technologies | 2 | Active |
| US8658514B2 | Method for manufacturing a semiconductor-on-insulator structure having low electrical losses, and corresponding structure | Electricity | 1 | Active |
| US11637542B2 | Heterostructure and method of fabrication | Emerging Cross-Sectional Technologies | 1 | Active |
| US11373898B2 | Method for manufacturing a semiconductor on insulator type structure by layer transfer | Electricity | 0 | Active |
| US12101080B2 | Heterostructure and method of fabrication | Emerging Cross-Sectional Technologies | 0 | Active |
| US8946053B2 | Method for reducing irregularities at the surface of a layer transferred from a source substrate to a glass-based support substrate | Electricity | 0 | Active |
| US9293473B2 | Method for manufacturing a semiconductor on insulator structure having low electrical losses | Electricity | 0 | Active |
| US11595020B2 | Heterostructure and method of fabrication | Emerging Cross-Sectional Technologies | 0 | Active |
| US8518799B2 | Process of making semiconductor on glass substrates with a stiffening layer | Electricity | 0 | Active |
| US8772875B2 | Semiconductor on glass substrate with stiffening layer | Electricity | 0 | Active |
| US11205702B2 | Method for manufacturing a structure for forming a tridimensional monolithic integrated circuit | Electricity | 0 | Active |
| US12362226B2 | Method for forming a handling substrate for a composite structure intended for RF applications and handling substrate | Electricity | 0 | Active |
| US7919391B2 | Methods for preparing a bonding surface of a semiconductor wafer | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.