Interconnection designs using sidewall image transfer (SIT)
US8962483B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.