Bad block reconfiguration in nonvolatile memory
US8966330B1 · kind B1 · utility
11Cited by
21References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2014 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | May 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.