Methods for manufacturing metal gates

US8987080B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Xinliang Lu · Fremont, US
• Seshadri Ganguli · Sunnyvale, US
• Atif Noori · Saratoga, US
• Maitreyee Mahajani · Saratoga, US
• Shih Chung Chen · Hsinchu, TW
• Yu Lei · Belmont, US
• Xinyu Fu · Pleasanton, US
• Wei V. Tang · Santa Clara, US
• Srinivas Gandikota · Santa Clara, US

Key dates

• Filing date: Apr 18, 2013
• Grant date: Mar 24, 2015
• Expiry date: Apr 18, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0193
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.