Method for using nanoparticles to make uniform discrete floating gate layer
US8987802B2 · kind B2 · utility
3Cited by
28References
5Claims
0Family size
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Key dates
| Filing date | Feb 28, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.