Semiconductor wafer with reduced thickness variation and method for fabricating same
US8987898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2011 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Jun 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor wafer comprises a plurality of solder bumps for providing device contacts formed over a functional region of the semiconductor wafer, and one or more support rings surrounding the functional region. The one or more support rings and the plurality of solder bumps are formed so as to have substantially matching heights. The presence of the one or more support rings causes the semiconductor wafer to have a substantially uniform thickness in the functional region after a thinning process is performed on the semiconductor wafer. A method for fabricating the semiconductor wafer comprises forming the plurality of solder bumps over the functional region, and forming the one or more support rings surrounding the functional region before performing the thinning process on the semiconductor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.